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Intel: application of high-k dielectrics will reduce leakage currents by 100 times!

Intel has made a significant breakthrough in the use of new materials for chip production, Intel reports. According to this statement, the use of new materials will significantly reduce current leakage, and therefore significantly reduce the power consumption of microcircuits and their heat dissipation.

So, already in 2021, Intel intends to start using special high-k dielectrics in the gates of transistor junctions, which, according to experts, will reduce current leakage by at least 100 times! According to the well-known Moore’s Law, the number of transistors in processors by that time may well approach 1 billion. It is planned that in 2021 the company will switch to 45 nm process technology. It is at this stage that the usual silicon dioxide in the gates will be replaced by an as yet unnamed high-k dielectric. Along with this, the company also plans to move away from the use of polycrystalline silicon additives in the formation of the gate electrode of the transistor, and start using two different metals, respectively, to create junctions in NMOS or PMOS types of transistors.

The essence of the current leakage problem, to outline it schematically, is as follows: the thickness of the silicon dioxide layer, which is now used in the gates of transistors as a dielectric, has been reduced to 5 atoms, which in turn leads to electron tunneling through the oxide layer in the “on” condition and increased energy consumption. The transition to the use of high-k materials leads to the fact that the current flowing through the transition in the on state only slightly exceeds this indicator in the off state, and, accordingly, we can talk about a significant decrease in leakage.

The very effect of reducing leaks from the use of high-k oxides, as such, has been known for a long time, however, scientists are still looking for materials that are most suitable for such purposes. The use of already known high-k materials, for example, hafnium oxide, zirconium oxide and others, usually leads to a significant decrease in the current in the channel under the gate dielectric, plus, leads to serious problems when setting the gate operating threshold voltage, especially in PMOS-type transistors.

Details on the technology for the new high-k dielectrics are expected to be presented by Robert Chau, Lead Developer at Intel’s Hillsboro Lab, Oregon, on Thursday at the International Gate Insulator Workshop in Tokyo. The presentation describes in detail the creation of NMOS and PMOS transistors with a physical gate length of about 80 nm and the use of dielectrics about 1.4 nm thick (14 Angstroms).

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